1// Copyright (C) 2016 The Qt Company Ltd.
2// Copyright (C) 2016 Intel Corporation.
3// SPDX-License-Identifier: LicenseRef-Qt-Commercial OR LGPL-3.0-only OR GPL-2.0-only OR GPL-3.0-only
4
5
6#if 0
7#pragma qt_class(QtProcessorDetection)
8#pragma qt_sync_skip_header_check
9#pragma qt_sync_stop_processing
10#endif
11
12#ifndef QPROCESSORDETECTION_H
13#define QPROCESSORDETECTION_H
14
15/*
16 This file uses preprocessor #defines to set various Q_PROCESSOR_* #defines
17 based on the following patterns:
18
19 Q_PROCESSOR_{FAMILY}
20 Q_PROCESSOR_{FAMILY}_{VARIANT}
21 Q_PROCESSOR_{FAMILY}_{REVISION}
22
23 The first is always defined. Defines for the various revisions/variants are
24 optional and usually dependent on how the compiler was invoked. Variants
25 that are a superset of another should have a define for the superset.
26
27 In addition to the processor family, variants, and revisions, we also set
28 Q_BYTE_ORDER appropriately for the target processor. For bi-endian
29 processors, we try to auto-detect the byte order using the __BIG_ENDIAN__,
30 __LITTLE_ENDIAN__, or __BYTE_ORDER__ preprocessor macros.
31
32 Note: when adding support for new processors, be sure to update
33 config.tests/arch/arch.cpp to ensure that configure can detect the target
34 and host architectures.
35*/
36
37/* Machine byte-order, reuse preprocessor provided macros when available */
38#if defined(__ORDER_BIG_ENDIAN__)
39# define Q_BIG_ENDIAN __ORDER_BIG_ENDIAN__
40#else
41# define Q_BIG_ENDIAN 4321
42#endif
43#if defined(__ORDER_LITTLE_ENDIAN__)
44# define Q_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__
45#else
46# define Q_LITTLE_ENDIAN 1234
47#endif
48
49/*
50 Alpha family, no revisions or variants
51
52 Alpha is bi-endian, use endianness auto-detection implemented below.
53*/
54#if defined(__alpha__) || defined(_M_ALPHA)
55# define Q_PROCESSOR_ALPHA
56// Q_BYTE_ORDER not defined, use endianness auto-detection
57
58/*
59 ARM family, known revisions: V5, V6, V7, V8
60
61 ARM is bi-endian, detect using __ARMEL__ or __ARMEB__, falling back to
62 auto-detection implemented below.
63*/
64#elif defined(__arm__) || defined(__TARGET_ARCH_ARM) || defined(_M_ARM) || defined(_M_ARM64) || defined(__aarch64__) || defined(__ARM64__)
65# if defined(__aarch64__) || defined(__ARM64__) || defined(_M_ARM64)
66# define Q_PROCESSOR_ARM_64
67# define Q_PROCESSOR_WORDSIZE 8
68# else
69# define Q_PROCESSOR_ARM_32
70# endif
71# if defined(__ARM_ARCH) && __ARM_ARCH > 1
72# define Q_PROCESSOR_ARM __ARM_ARCH
73# elif defined(__TARGET_ARCH_ARM) && __TARGET_ARCH_ARM > 1
74# define Q_PROCESSOR_ARM __TARGET_ARCH_ARM
75# elif defined(_M_ARM) && _M_ARM > 1
76# define Q_PROCESSOR_ARM _M_ARM
77# elif defined(__ARM64_ARCH_8__) \
78 || defined(__aarch64__) \
79 || defined(__ARMv8__) \
80 || defined(__ARMv8_A__) \
81 || defined(_M_ARM64)
82# define Q_PROCESSOR_ARM 8
83# elif defined(__ARM_ARCH_7__) \
84 || defined(__ARM_ARCH_7A__) \
85 || defined(__ARM_ARCH_7R__) \
86 || defined(__ARM_ARCH_7M__) \
87 || defined(__ARM_ARCH_7S__) \
88 || defined(_ARM_ARCH_7) \
89 || defined(__CORE_CORTEXA__)
90# define Q_PROCESSOR_ARM 7
91# elif defined(__ARM_ARCH_6__) \
92 || defined(__ARM_ARCH_6J__) \
93 || defined(__ARM_ARCH_6T2__) \
94 || defined(__ARM_ARCH_6Z__) \
95 || defined(__ARM_ARCH_6K__) \
96 || defined(__ARM_ARCH_6ZK__) \
97 || defined(__ARM_ARCH_6M__)
98# define Q_PROCESSOR_ARM 6
99# elif defined(__ARM_ARCH_5TEJ__) \
100 || defined(__ARM_ARCH_5TE__)
101# define Q_PROCESSOR_ARM 5
102# else
103# define Q_PROCESSOR_ARM 0
104# endif
105# if Q_PROCESSOR_ARM >= 8
106# define Q_PROCESSOR_ARM_V8
107# endif
108# if Q_PROCESSOR_ARM >= 7
109# define Q_PROCESSOR_ARM_V7
110# endif
111# if Q_PROCESSOR_ARM >= 6
112# define Q_PROCESSOR_ARM_V6
113# endif
114# if Q_PROCESSOR_ARM >= 5
115# define Q_PROCESSOR_ARM_V5
116# else
117# error "ARM architecture too old"
118# endif
119# if defined(__ARMEL__) || defined(_M_ARM64)
120# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
121# elif defined(__ARMEB__)
122# define Q_BYTE_ORDER Q_BIG_ENDIAN
123# else
124// Q_BYTE_ORDER not defined, use endianness auto-detection
125#endif
126
127/*
128 AVR32 family, no revisions or variants
129
130 AVR32 is big-endian.
131*/
132// #elif defined(__avr32__)
133// # define Q_PROCESSOR_AVR32
134// # define Q_BYTE_ORDER Q_BIG_ENDIAN
135
136/*
137 Blackfin family, no revisions or variants
138
139 Blackfin is little-endian.
140*/
141// #elif defined(__bfin__)
142// # define Q_PROCESSOR_BLACKFIN
143// # define Q_BYTE_ORDER Q_LITTLE_ENDIAN
144
145/*
146 PA-RISC family, no revisions or variants
147
148 PA-RISC is big-endian.
149*/
150#elif defined(__hppa__)
151# define Q_PROCESSOR_HPPA
152# define Q_BYTE_ORDER Q_BIG_ENDIAN
153
154/*
155 X86 family, known variants: 32- and 64-bit
156
157 X86 is little-endian.
158*/
159#elif defined(__i386) || defined(__i386__) || defined(_M_IX86)
160# define Q_PROCESSOR_X86_32
161# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
162# define Q_PROCESSOR_WORDSIZE 4
163
164/*
165 * We define Q_PROCESSOR_X86 == 6 for anything above a equivalent or better
166 * than a Pentium Pro (the processor whose architecture was called P6) or an
167 * Athlon.
168 *
169 * All processors since the Pentium III and the Athlon 4 have SSE support, so
170 * we use that to detect. That leaves the original Athlon, Pentium Pro and
171 * Pentium II.
172 */
173
174# if defined(_M_IX86)
175# define Q_PROCESSOR_X86 (_M_IX86/100)
176# elif defined(__i686__) || defined(__athlon__) || defined(__SSE__) || defined(__pentiumpro__)
177# define Q_PROCESSOR_X86 6
178# elif defined(__i586__) || defined(__k6__) || defined(__pentium__)
179# define Q_PROCESSOR_X86 5
180# elif defined(__i486__) || defined(__80486__)
181# define Q_PROCESSOR_X86 4
182# else
183# define Q_PROCESSOR_X86 3
184# endif
185
186#elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
187# define Q_PROCESSOR_X86 6
188# define Q_PROCESSOR_X86_64
189# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
190# define Q_PROCESSOR_WORDSIZE 8
191
192/*
193 Itanium (IA-64) family, no revisions or variants
194
195 Itanium is bi-endian, use endianness auto-detection implemented below.
196*/
197#elif defined(__ia64) || defined(__ia64__) || defined(_M_IA64)
198# define Q_PROCESSOR_IA64
199# define Q_PROCESSOR_WORDSIZE 8
200// Q_BYTE_ORDER not defined, use endianness auto-detection
201
202/*
203 LoongArch family, known variants: 32- and 64-bit
204
205 LoongArch is little-endian.
206*/
207#elif defined(__loongarch__)
208# define Q_PROCESSOR_LOONGARCH
209# if __loongarch_grlen == 64
210# define Q_PROCESSOR_LOONGARCH_64
211# else
212# define Q_PROCESSOR_LOONGARCH_32
213# endif
214# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
215
216/*
217 Motorola 68000 family, no revisions or variants
218
219 M68K is big-endian.
220*/
221#elif defined(__m68k__)
222# define Q_PROCESSOR_M68K
223# define Q_BYTE_ORDER Q_BIG_ENDIAN
224
225/*
226 MIPS family, known revisions: I, II, III, IV, 32, 64
227
228 MIPS is bi-endian, use endianness auto-detection implemented below.
229*/
230#elif defined(__mips) || defined(__mips__) || defined(_M_MRX000)
231# define Q_PROCESSOR_MIPS
232# if defined(_MIPS_ARCH_MIPS1) || (defined(__mips) && __mips - 0 >= 1)
233# define Q_PROCESSOR_MIPS_I
234# endif
235# if defined(_MIPS_ARCH_MIPS2) || (defined(__mips) && __mips - 0 >= 2)
236# define Q_PROCESSOR_MIPS_II
237# endif
238# if defined(_MIPS_ARCH_MIPS3) || (defined(__mips) && __mips - 0 >= 3)
239# define Q_PROCESSOR_MIPS_III
240# endif
241# if defined(_MIPS_ARCH_MIPS4) || (defined(__mips) && __mips - 0 >= 4)
242# define Q_PROCESSOR_MIPS_IV
243# endif
244# if defined(_MIPS_ARCH_MIPS5) || (defined(__mips) && __mips - 0 >= 5)
245# define Q_PROCESSOR_MIPS_V
246# endif
247# if defined(_MIPS_ARCH_MIPS32) || defined(__mips32) || (defined(__mips) && __mips - 0 >= 32)
248# define Q_PROCESSOR_MIPS_32
249# endif
250# if defined(_MIPS_ARCH_MIPS64) || defined(__mips64)
251# define Q_PROCESSOR_MIPS_64
252# define Q_PROCESSOR_WORDSIZE 8
253# endif
254# if defined(__MIPSEL__)
255# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
256# elif defined(__MIPSEB__)
257# define Q_BYTE_ORDER Q_BIG_ENDIAN
258# else
259// Q_BYTE_ORDER not defined, use endianness auto-detection
260# endif
261
262/*
263 Power family, known variants: 32- and 64-bit
264
265 There are many more known variants/revisions that we do not handle/detect.
266 See http://en.wikipedia.org/wiki/Power_Architecture
267 and http://en.wikipedia.org/wiki/File:PowerISA-evolution.svg
268
269 Power is bi-endian, use endianness auto-detection implemented below.
270*/
271#elif defined(__ppc__) || defined(__ppc) || defined(__powerpc__) \
272 || defined(_ARCH_COM) || defined(_ARCH_PWR) || defined(_ARCH_PPC) \
273 || defined(_M_MPPC) || defined(_M_PPC)
274# define Q_PROCESSOR_POWER
275# if defined(__ppc64__) || defined(__powerpc64__) || defined(__64BIT__)
276# define Q_PROCESSOR_POWER_64
277# define Q_PROCESSOR_WORDSIZE 8
278# else
279# define Q_PROCESSOR_POWER_32
280# endif
281// Q_BYTE_ORDER not defined, use endianness auto-detection
282
283/*
284 RISC-V family, known variants: 32- and 64-bit
285
286 RISC-V is little-endian.
287*/
288#elif defined(__riscv)
289# define Q_PROCESSOR_RISCV
290# if __riscv_xlen == 64
291# define Q_PROCESSOR_RISCV_64
292# else
293# define Q_PROCESSOR_RISCV_32
294# endif
295# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
296
297/*
298 S390 family, known variant: S390X (64-bit)
299
300 S390 is big-endian.
301*/
302#elif defined(__s390__)
303# define Q_PROCESSOR_S390
304# if defined(__s390x__)
305# define Q_PROCESSOR_S390_X
306# endif
307# define Q_BYTE_ORDER Q_BIG_ENDIAN
308
309/*
310 SuperH family, optional revision: SH-4A
311
312 SuperH is bi-endian, use endianness auto-detection implemented below.
313*/
314// #elif defined(__sh__)
315// # define Q_PROCESSOR_SH
316// # if defined(__sh4a__)
317// # define Q_PROCESSOR_SH_4A
318// # endif
319// Q_BYTE_ORDER not defined, use endianness auto-detection
320
321/*
322 SPARC family, optional revision: V9
323
324 SPARC is big-endian only prior to V9, while V9 is bi-endian with big-endian
325 as the default byte order. Assume all SPARC systems are big-endian.
326*/
327#elif defined(__sparc__)
328# define Q_PROCESSOR_SPARC
329# if defined(__sparc_v9__) || defined(__sparcv9)
330# define Q_PROCESSOR_SPARC_V9
331# endif
332# if defined(__sparc64__)
333# define Q_PROCESSOR_SPARC_64
334# endif
335# define Q_BYTE_ORDER Q_BIG_ENDIAN
336
337// -- Web Assembly --
338#elif defined(__EMSCRIPTEN__)
339# define Q_PROCESSOR_WASM
340# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
341# define Q_PROCESSOR_WORDSIZE 8
342#ifdef QT_COMPILER_SUPPORTS_SSE2
343# define Q_PROCESSOR_X86 6 // enables SIMD support
344# define Q_PROCESSOR_X86_64 // wasm64
345# define Q_PROCESSOR_WASM_64
346#endif
347
348#endif
349
350/*
351 NOTE:
352 GCC 4.6 added __BYTE_ORDER__, __ORDER_BIG_ENDIAN__, __ORDER_LITTLE_ENDIAN__
353 and __ORDER_PDP_ENDIAN__ in SVN r165881. If you are using GCC 4.6 or newer,
354 this code will properly detect your target byte order; if you are not, and
355 the __LITTLE_ENDIAN__ or __BIG_ENDIAN__ macros are not defined, then this
356 code will fail to detect the target byte order.
357*/
358// Some processors support either endian format, try to detect which we are using.
359#if !defined(Q_BYTE_ORDER)
360# if defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == Q_BIG_ENDIAN || __BYTE_ORDER__ == Q_LITTLE_ENDIAN)
361// Reuse __BYTE_ORDER__ as-is, since our Q_*_ENDIAN #defines match the preprocessor defaults
362# define Q_BYTE_ORDER __BYTE_ORDER__
363# elif defined(__BIG_ENDIAN__) || defined(_big_endian__) || defined(_BIG_ENDIAN)
364# define Q_BYTE_ORDER Q_BIG_ENDIAN
365# elif defined(__LITTLE_ENDIAN__) || defined(_little_endian__) || defined(_LITTLE_ENDIAN)
366# define Q_BYTE_ORDER Q_LITTLE_ENDIAN
367# else
368# error "Unable to determine byte order!"
369# endif
370#endif
371
372/*
373 Size of a pointer and the machine register size. We detect a 64-bit system by:
374 * GCC and compatible compilers (Clang, ICC on OS X and Windows) always define
375 __SIZEOF_POINTER__. This catches all known cases of ILP32 builds on 64-bit
376 processors.
377 * Most other Unix compilers define __LP64__ or _LP64 on 64-bit mode
378 (Long and Pointer 64-bit)
379 * If Q_PROCESSOR_WORDSIZE was defined above, it's assumed to match the pointer
380 size.
381 Otherwise, we assume to be 32-bit and then check in qglobal.cpp that it is right.
382*/
383
384#if defined __SIZEOF_POINTER__
385# define QT_POINTER_SIZE __SIZEOF_POINTER__
386#elif defined(__LP64__) || defined(_LP64)
387# define QT_POINTER_SIZE 8
388#elif defined(Q_PROCESSOR_WORDSIZE)
389# define QT_POINTER_SIZE Q_PROCESSOR_WORDSIZE
390#else
391# define QT_POINTER_SIZE 4
392#endif
393
394/*
395 Define Q_PROCESSOR_WORDSIZE to be the size of the machine's word (usually,
396 the size of the register). On some architectures where a pointer could be
397 smaller than the register, the macro is defined above.
398
399 Falls back to QT_POINTER_SIZE if not set explicitly for the platform.
400*/
401#ifndef Q_PROCESSOR_WORDSIZE
402# define Q_PROCESSOR_WORDSIZE QT_POINTER_SIZE
403#endif
404
405
406#endif // QPROCESSORDETECTION_H
407

source code of qtbase/src/corelib/global/qprocessordetection.h